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  ? 2007 microchip technology inc. preliminary ds39894a PIC18F8723 family data sheet 64/80-pin, 1-mbit, enhanced flash microcontrollers with 12-bit a/d and nanowatt technology www.datasheet.in
ds39894a-page ii preliminary ? 2007 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, micro id , mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, linear active thermistor, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip tec hnology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are tr ademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2007, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 1 PIC18F8723 family peripheral highlights: ? 12-bit, up to 16-channel analog-to-digital converter module (a/d): - auto-acquisition capability - conversion available during sleep ? two master synchronous serial port (mssp) modules supporting 2/3/4-wire spi (all four modes) and i 2 c? master and slave modes ? two capture/compare/pwm (ccp) modules ? three enhanced capture/compare/pwm (eccp) modules: - one, two or four pwm outputs - selectable polarity - programmable dead time - auto-shutdown and auto-restart ? two enhanced addressable usart modules: - supports rs-485, rs-232 and lin 1.2 - auto-wake-up on start bit - auto-baud detect ? dual analog comparators with input multiplexing ? high-current sink/source 25 ma/25 ma ? four programmable external interrupts ? four input change interrupts external memory interface: ? address capability of up to 2 mbytes ? 8-bit or 16-bit interface ? 8, 12, 16 and 20-bit address modes power-managed modes: ? run: cpu on, peripherals on ? idle: cpu off, peripherals on ? sleep: cpu off, peripherals off ? idle mode currents down to 15 a typical ? sleep current down to 0.2 a typical ? timer1 oscillator: 1.8 a, 32 khz, 2v ? watchdog timer: 2.1 a special microcontroller features: ? c compiler optimized architecture: - optional extended instruction set designed to optimize re-entrant code ? 100,000 erase/write cycle enhanced flash program memory typical ? 1,000,000 erase/write cycle data eeprom memory typical ? flash/data eeprom retention: 100 years typical ? self-programmable under software control ? priority levels for interrupts ? 8 x 8 single-cycle hardware multiplier ? extended watchdog timer (wdt): - programmable period from 4 ms to 131s ? single-supply in-circuit serial programming? (icsp?) via two pins ? in-circuit debug (icd) via two pins ? wide operating voltage range: 2.0v to 5.5v ? fail-safe clock monitor ? two-speed oscillator start-up ? nanowatt technology note: this document is supplemented by the ?pic18f8722 family data sheet? (ds39646). see section 1.0 ?device overview? . device program memory data memory i/o 12-bit a/d (ch) ccp/ eccp (pwm) mssp eusart comparators timers 8/16-bit external bus flash (bytes) # single-word instructions sram (bytes) eeprom (bytes) spi master i 2 c? pic18f6628 96k 49152 3936 1024 54 12 2/3 2 y y 2 2 2/3 n pic18f6723 128k 65536 3936 1024 54 12 2/3 2 y y 2 2 2/3 n pic18f8628 96k 49152 3936 1024 70 16 2/3 2 y y 2 2 2/3 y PIC18F8723 128k 65536 3936 1024 70 16 2/3 2 y y 2 2 2/3 y 64/80-pin, 1-mbit, enhanced flash microcontrollers with 12-bit a/d and nanowatt technology www.datasheet.in
PIC18F8723 ds39894a-page 2 preliminary ? 2007 microchip technology inc. pin diagrams note 1: the eccp2/p2a pin placement is determined by the ccp2mx configuration bit. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 38 37 36 35 34 33 50 49 17 18 19 20 21 22 23 24 25 26 re2/cs /p2b re3/p3c re4/p3b re5/p1c re6/p1b re7/eccp2 (1) /p2a (1) rd0/psp0 v dd v ss rd1/psp1 rd2/psp2 rd3/psp3 rd4/psp4/sdo2 rd5/psp5/sdi2/sda2 rd6/psp6/sck2/scl2 rd7/psp7/ss2 re1/wr /p2c re0/rd /p2d rg0/eccp3/p3a rg1/tx2/ck2 rg2/rx2/dt2 rg3/ccp4/p3d rg5/mclr /v pp rg4/ccp5/p1d v ss v dd rf7/ss1 rf6/an11 rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out rb0/int0 rb1/int1 rb2/int2 rb3/int3 rb4/kbi0 rb5/kbi1/pgm rb6/kbi2/pgc v ss osc2/clko/ra6 osc1/clki/ra7 v dd rb7/kbi3/pgd rc4/sdi1/sda1 rc3/sck1/scl1 rc2/eccp1/p1a rf0/an5 rf1/an6/c2out av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v ss v dd ra4/t0cki ra5/an4/hlvdin rc1/t1osi/eccp2 (1) /p2a (1) rc0/t1oso/t13cki rc7/rx1/dt1 rc6/tx1/ck1 rc5/sdo1 15 16 31 40 39 27 28 29 30 32 48 47 46 45 44 43 42 41 54 53 52 51 58 57 56 55 60 59 64 63 62 61 64-pin tqfp pic18f6628 pic18f6723 www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 3 PIC18F8723 pin diagrams (continued) 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 re2/ad10/cs /p2b re3/ad11/p3c (2) re4/ad12/p3b (2) re5/ad13/p1c (2) re6/ad14/p1b (2) re7/ad15/eccp2 (1) /p2a (1) rd0/ad0/psp0 v dd v ss rd1/ad1/psp1 rd2/ad2/psp2 rd3/ad3/psp3 rd4/ad4/psp4/sdo2 rd5/ad5/psp5/sdi2/sda2 rd6/ad6/psp6/sck2/scl2 rd7/ad7/psp7/ss2 re1/ad9/wr /p2c re0/ad8/rd /p2d rg0/eccp3/p3a rg1/tx2/ck2 rg2/rx2/dt2 rg3/ccp4/p3d rg5/mclr /v pp rg4/ccp5/p1d v ss v dd rf7/ss1 rb0/int0 rb1/int1 rb2/int2 rb3/int3/eccp2 (1) /p2a (1) rb4/kbi0 rb5/kbi1/pgm rb6/kbi2/pgc v ss osc2/clko/ra6 osc1/clki/ra7 v dd rb7/kbi3/pgd rc4/sdi1/sda1 rc3/sck1/scl1 rc2/eccp1/p1a rf0/an5 rf1/an6/c2out av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/an1 ra0/an0 v ss v dd ra4/t0cki ra5/an4/hlvdin rc1/t1osi/eccp2 (1) /p2a (1) rc0/t1oso/t13cki rc7/rx1/dt1 rc6/tx1/ck1 rc5/sdo1 rj0/ale rj1/oe rh1/a17 rh0/a16 1 2 rh2/a18 rh3/a19 17 18 rh7/an15/p1b (2) rh6/an14/p1c (2) rh5/an13/p3b (2) rh4/an12/p3c (2) rj5/ce rj4/ba0 37 rj7/ub rj6/lb 50 49 rj2/wrl rj3/wrh 19 20 33 34 35 36 38 58 57 56 55 54 53 52 51 60 59 68 67 66 65 72 71 70 69 74 73 78 77 76 75 79 80 80-pin tqfp note 1: the eccp2/p2a pin placement is determined by the ccp2mx configuration bit and processor mode settings. 2: p1b, p1c, p3b and p3c pin placement is determined by the eccpmx configuration bit. rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out rf6/an11 pic18f8628 PIC18F8723 www.datasheet.in
PIC18F8723 ds39894a-page 4 preliminary ? 2007 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................. 7 2.0 12-bit analog-to-digital converter (a/d) module ............................................................................. .......................................... 29 3.0 special features of the cpu ................................................................................................. ..................................................... 39 4.0 electrical characteristics ................................................................................................. .......................................................... 41 5.0 packaging information....................................................................................................... ......................................................... 47 appendix a: revision history................................................................................................... ............................................................ 49 appendix b: device differences................................................................................................. .......................................................... 49 appendix c: conversion considerations .......................................................................................... ................................................... 50 appendix d: migration from baseline to enhanced devices........................................................................ ....................................... 50 appendix e: migration from mid-range to enhanced devices ....................................................................... .................................... 51 appendix f: migration from high-end to enhanced devices........................................................................ ...................................... 51 index .......................................................................................................................... .......................................................................... 53 the microchip web site ......................................................................................................... .............................................................. 55 customer change notification service ........................................................................................... ..................................................... 55 customer support ............................................................................................................... ................................................................. 55 reader response ................................................................................................................ ................................................................ 56 PIC18F8723 family product identification system................................................................................ .............................................. 57 www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 5 PIC18F8723 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. www.datasheet.in
PIC18F8723 ds39894a-page 6 preliminary ? 2007 microchip technology inc. notes: www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 7 PIC18F8723 family 1.0 device overview this document contains device-specific information for the following devices: the PIC18F8723 family of devices offers the advantages of all pic18 microcontrollers ? namely, high computational performance at an economical price ? with the addition of high-endurance, enhanced flash program memory. in addition to these features, the PIC18F8723 introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power-sensitive applications. 1.1 special features ? 12-bit a/d converter: the PIC18F8723 family implements a 12-bit a/d converter. a/d converters in both families incorporate programmable acquisi- tion time. this allows for a channel to be selected and a conversion to be initiated, without waiting for a sampling period and thus, reducing code overhead. 1.2 details on individual family members devices in the PIC18F8723 family are available in 64-pin and 80-pin packages. block diagrams for the two groups are shown in figure 1-1 and figure 1-2. the devices are differentiated from each other in the following ways: ? flash program memory (96 kbytes for pic18fx628 devices and 128 kbytes for pic18fx723). ? a/d channels (12 for pic18f6628/6723 devices and 16 for pic18f8628/8723 devices). ? i/o ports (seven bidirectional ports on pic18f6628/6723 devices and nine bidirectional ports on pic18f8628/8723 devices). ? external memory bus, configurable for 8 and 16-bit operation all other features for devices in this family are identical. these are summarized in table 1-1. the pinouts for all devices are listed in table 1-2 and table 1-3. like all microchip pic18 devices, members of the PIC18F8723 family are available as both standard and low-voltage devices. standard devices with enhanced flash memory, designated with an ?f? in the part number (such as pic18 f 6628), accommodate an operating v dd range of 4.2v to 5.5v. low-voltage parts, designated by ?lf? (such as pic18 lf 6628), function over an extended v dd range of 2.0v to 5.5v. ? pic18f6628 ? pic18lf6628 ? pic18f6723 ? pic18lf6723 ? pic18f8628 ? pic18lf8628 ? PIC18F8723 ? pic18lf8723 note: this data sheet documents only the devices? features and specifications that are in addition to the features and specifications of the pic18f8722 family devices. for information on the features and specifications shared by the PIC18F8723 family and pic18f8722 fam- ily devices, see the ?pic18f8722 family data sheet? (ds39646). www.datasheet.in
PIC18F8723 family ds39894a-page 8 preliminary ? 2007 microchip technology inc. table 1-1: device features features pic18f6628 pic18f6723 pic18f8628 PIC18F8723 operating frequency dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz dc ? 40 mhz program memory (bytes) 96k 128k 96k 128k program memory (instructions) 49152 65536 49152 65536 data memory (bytes) 3936 3936 3936 3936 data eeprom memory (bytes) 1024 1024 1024 1024 interrupt sources 28282929 i/o ports ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g, h , j ports a, b, c, d, e, f, g, h, j timers 5 5 5 5 capture/compare/pwm modules 2222 enhanced capture/compare/ pwm modules 3333 enhanced usart 2 2 2 2 serial communications mssp, enhanced usart mssp, enhanced usart mssp, enhanced usart mssp, enhanced usart parallel communications (psp) yes yes yes yes 12-bit analog-to-digital module 12 input channels 12 input channels 16 input channels 16 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt por, bor, reset instruction, stack full, stack underflow (pwrt, ost), mclr (optional), wdt programmable high/low-voltage detect yes yes yes yes programmable brown-out reset yes yes yes yes instruction set 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled 75 instructions; 83 with extended instruction set enabled packages 64-pin tqfp 64-pin tqfp 80-pin tqfp 80-pin tqfp www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 9 PIC18F8723 family figure 1-1: pic18f6628/6723 (64-pin) block diagram instruction decode and control porta data latch data memory (3.9 kbytes) address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> address latch program memory (48/64/96/128 data latch 20 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 pclatu pcu note 1: see table 1-2 for i/o port pin descriptions. 2: rg5 is only available when m clr functionality is disabled. 3: osc1/clki and osc2/clko are only available in select oscillator modes and when these pins are not being used as digital i/o. for additional information, refer to section 2.0 ?oscillator configurations? of the ?pic18f8722 family data sheet? (ds39646). eusart1 comparators mssp1 timer2 timer1 timer3 timer0 hlvd eccp1 bor adc 12-bit w instruction bus <16> stkptr bank 8 state machine control signals decode 8 8 power-up timer oscillator start-up timer power-on reset watchdog timer osc1 (3) osc2 (3) v dd , brown-out reset internal oscillator fail-safe clock monitor precision reference band gap v ss mclr (2) block intrc oscillator 8 mhz oscillator single-supply programming in-circuit debugger t1osi t1oso eusart2 eccp2 rom latch eccp3 mssp2 ccp4 ccp5 portc portd porte portf portg ra0:ra7 (1) rc0:rc7 (1) rd0:rd7 (1) re0:re7 (1) rf0:rf7 (1) rg0:rg5 (1,2) portb rb0:rb7 (1) timer4 kbytes) www.datasheet.in
PIC18F8723 family ds39894a-page 10 preliminary ? 2007 microchip technology inc. figure 1-2: pic18f8628/8723 (80-pin) block diagram prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> 8 8 3 w 8 8 8 power-up timer oscillator start-up timer power-on reset watchdog timer osc1 (3) osc2 (3) v dd , brown-out reset internal oscillator fail-safe clock monitor precision reference band gap v ss mclr (2) block intrc oscillator 8 mhz oscillator single-supply programming in-circuit debugger t1osi t1oso instruction decode & control data latch data memory (3.9 kbytes) address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4124 pch pcl pclath 8 31 level stack program counter address latch program memory (48/64/96/128 data latch 20 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 rom latch pclatu pcu instruction bus <16> stkptr bank state machine control signals decode system bus interface ad15:ad0, a19:a16 (multiplexed with portd, porte and porth) porta portc portd porte portf portg ra0:ra7 (1) rc0:rc7 (1) rd0:rd7 (1) re0:re7 (1) rf0:rf7 (1) rg0:rg5 (1,2) portb rb0:rb7 (1) porth rh0:rh7 (1) portj rj0:rj7 (1) eusart1 comparators mssp1 timer2 timer1 timer3 timer0 hlvd eccp1 bor adc 12-bit eusart2 eccp2 eccp3 mssp2 ccp4 ccp5 timer4 note 1: see table 1-3 for i/o port pin descriptions. 2: rg5 is only available when mclr functionality is disabled. 3: osc1/clki and osc2/clko are only available in select oscillator modes and when these pins are not being used as digital i/o. for additional information, refer to section 2.0 ?oscillator configurations? of the ?pic18f8722 family data sheet? (ds39646). kbytes) www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 11 PIC18F8723 family table 1-2: pic18f6628/6723 (64-pin) pinout i/o descriptions pin name pin number pin type buffer type description tqfp rg5/mclr /v pp rg5 mclr v pp 7 i i p st st master clear (input) or programming voltage (input). digital input. master clear (reset) input. this pin is an active-low reset to the device. programming voltage input. osc1/clki/ra7 osc1 clki ra7 39 i i i/o st cmos ttl oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode, cmos otherwise. external clock source input. always associated with pin function osc1. (see related osc1/clki, osc2/clko pins.) general purpose i/o pin. osc2/clko/ra6 osc2 clko ra6 40 o o i/o ? ? ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c? = i 2 c/smbus input buffer note 1: default assignment for eccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared. www.datasheet.in
PIC18F8723 family ds39894a-page 12 preliminary ? 2007 microchip technology inc. porta is a bidirectional i/o port. ra0/an0 ra0 an0 24 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 23 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref - ra2 an2 v ref - 22 i/o i i ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 21 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 28 i/o i st st digital i/o. timer0 external clock input. ra5/an4/hlvdin ra5 an4 hlvdin 27 i/o i i ttl analog analog digital i/o. analog input 4. high/low-voltage detect input. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. table 1-2: pic18f6628/6723 (64-pin) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c? = i 2 c/smbus input buffer note 1: default assignment for eccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared. www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 13 PIC18F8723 family portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0/flt0 rb0 int0 flt0 48 i/o i i ttl st st digital i/o. external interrupt 0. pwm fault input for eccpx. rb1/int1 rb1 int1 47 i/o i ttl st digital i/o. external interrupt 1. rb2/int2 rb2 int2 46 i/o i ttl st digital i/o. external interrupt 2. rb3/int3 rb3 int3 45 i/o i ttl st digital i/o. external interrupt 3. rb4/kbi0 rb4 kbi0 44 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb5/kbi1/pgm rb5 kbi1 pgm 43 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. low-voltage icsp? programming enable pin. rb6/kbi2/pgc rb6 kbi2 pgc 42 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 37 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-2: pic18f6628/6723 (64-pin) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c? = i 2 c/smbus input buffer note 1: default assignment for eccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared. www.datasheet.in
PIC18F8723 family ds39894a-page 14 preliminary ? 2007 microchip technology inc. portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 30 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/eccp2/ p2a rc1 t1osi eccp2 (1) p2a (1) 29 i/o i i/o o st cmos st ? digital i/o. timer1 oscillator input. enhanced capture 2 input/compare 2 output/ pwm2 output. eccp2 pwm output a. rc2/eccp1/p1a rc2 eccp1 p1a 33 i/o i/o o st st ? digital i/o. enhanced capture 1 input/compare 1 output/ pwm1 output. eccp1 pwm output a. rc3/sck1/scl1 rc3 sck1 scl1 34 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi1/sda1 rc4 sdi1 sda1 35 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo1 rc5 sdo1 36 i/o o st ? digital i/o. spi data out. rc6/tx1/ck1 rc6 tx1 ck1 31 i/o o i/o st ? st digital i/o. eusart1 asynchronous transmit. eusart1 synchronous clock (see related rx1/dt1). rc7/rx1/dt1 rc7 rx1 dt1 32 i/o i i/o st st st digital i/o. eusart1 asynchronous receive. eusart1 synchronous data (see related tx1/ck1). table 1-2: pic18f6628/6723 (64-pin) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c? = i 2 c/smbus input buffer note 1: default assignment for eccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared. www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 15 PIC18F8723 family portd is a bidirectional i/o port. rd0/psp0 rd0 psp0 58 i/o i/o st ttl digital i/o. parallel slave port data. rd1/psp1 rd1 psp1 55 i/o i/o st ttl digital i/o. parallel slave port data. rd2/psp2 rd2 psp2 54 i/o i/o st ttl digital i/o. parallel slave port data. rd3/psp3 rd3 psp3 53 i/o i/o st ttl digital i/o. parallel slave port data. rd4/psp4/sdo2 rd4 psp4 sdo2 52 i/o i/o o st ttl ? digital i/o. parallel slave port data. spi data out. rd5/psp5/sdi2/ sda2 rd5 psp5 sdi2 sda2 51 i/o i/o i i/o st ttl st i 2 c/smb digital i/o. parallel slave port data. spi data in. i 2 c? data i/o. rd6/psp6/sck2/ scl2 rd6 psp6 sck2 scl2 50 i/o i/o i/o i/o st ttl st i 2 c/smb digital i/o. parallel slave port data. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c mode. rd7/psp7/ss2 rd7 psp7 ss2 49 i/o i/o i st ttl ttl digital i/o. parallel slave port data. spi slave select input. table 1-2: pic18f6628/6723 (64-pin) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c? = i 2 c/smbus input buffer note 1: default assignment for eccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared. www.datasheet.in
PIC18F8723 family ds39894a-page 16 preliminary ? 2007 microchip technology inc. porte is a bidirectional i/o port. re0/rd /p2d re0 rd p2d 2 i/o i o st ttl ? digital i/o. read control for parallel slave port. eccp2 pwm output d. re1/wr /p2c re1 wr p2c 1 i/o i o st ttl ? digital i/o. write control for parallel slave port. eccp2 pwm output c. re2/cs /p2b re2 cs p2b 64 i/o i o st ttl ? digital i/o. chip select control for parallel slave port. eccp2 pwm output b. re3/p3c re3 p3c 63 i/o o st ? digital i/o. eccp3 pwm output c. re4/p3b re4 p3b 62 i/o o st ? digital i/o. eccp3 pwm output b. re5/p1c re5 p1c 61 i/o o st ? digital i/o. eccp1 pwm output c. re6/p1b re6 p1b 60 i/o o st ? digital i/o. eccp1 pwm output b. re7/eccp2/p2a re7 eccp2 (2) p2a (2) 59 i/o i/o o st st ? digital i/o. enhanced capture 2 input/compare 2 output/ pwm2 output. eccp2 pwm output a. table 1-2: pic18f6628/6723 (64-pin) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c? = i 2 c/smbus input buffer note 1: default assignment for eccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared. www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 17 PIC18F8723 family portf is a bidirectional i/o port. rf0/an5 rf0 an5 18 i/o i st analog digital i/o. analog input 5. rf1/an6/c2out rf1 an6 c2out 17 i/o i o st analog ? digital i/o. analog input 6. comparator 2 output. rf2/an7/c1out rf2 an7 c1out 16 i/o i o st analog ? digital i/o. analog input 7. comparator 1 output. rf3/an8 rf3 an8 15 i/o i st analog digital i/o. analog input 8. rf4/an9 rf4 an9 14 i/o i st analog digital i/o. analog input 9. rf5/an10/cv ref rf5 an10 cv ref 13 i/o i o st analog analog digital i/o. analog input 10. comparator reference voltage output. rf6/an11 rf6 an11 12 i/o i st analog digital i/o. analog input 11. rf7/ss1 rf7 ss1 11 i/o i st ttl digital i/o. spi slave select input. table 1-2: pic18f6628/6723 (64-pin) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c? = i 2 c/smbus input buffer note 1: default assignment for eccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared. www.datasheet.in
PIC18F8723 family ds39894a-page 18 preliminary ? 2007 microchip technology inc. portg is a bidirectional i/o port. rg0/eccp3/p3a rg0 eccp3 p3a 3 i/o i/o o st st ? digital i/o. enhanced capture 3 input/compare 3 output/ pwm3 output. eccp3 pwm output a. rg1/tx2/ck2 rg1 tx2 ck2 4 i/o o i/o st ? st digital i/o. eusart2 asynchronous transmit. eusart2 synchronous clock (see related rx2/dt2). rg2/rx2/dt2 rg2 rx2 dt2 5 i/o i i/o st st st digital i/o. eusart2 asynchronous receive. eusart2 synchronous data (see related tx2/ck2). rg3/ccp4/p3d rg3 ccp4 p3d 6 i/o i/o o st st ? digital i/o. capture 4 input/compare 4 output/pwm4 output. eccp3 pwm output d. rg4/ccp5/p1d rg4 ccp5 p1d 8 i/o i/o o st st ? digital i/o. capture 5 input/compare 5 output/pwm5 output. eccp1 pwm output d. rg5 see rg5/mclr /v pp pin. v ss 9, 25, 41, 56 p ? ground reference for logic and i/o pins. v dd 10, 26, 38, 57 p ? positive supply for logic and i/o pins. av ss 20 p ? ground reference for analog modules. av dd 19 p ? positive supply for analog modules. table 1-2: pic18f6628/6723 (64-pin) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c? = i 2 c/smbus input buffer note 1: default assignment for eccp2 when configuration bit, ccp2mx, is set. 2: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared. www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 19 PIC18F8723 family table 1-3: pic18f8628/8723 (80-pin) pinout i/o descriptions pin name pin number pin type buffer type description tqfp rg5/mclr /v pp rg5 mclr v pp 9 i i p st st master clear (input) or programming voltage (input). digital input. master clear (reset) input. this pin is an active-low reset to the device. programming voltage input. osc1/clki/ra7 osc1 clki ra7 49 i i i/o st cmos ttl oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in rc mode, cmos otherwise. external clock source input. always associated with pin function osc1. (see related osc1/clki, osc2/clko pins.) general purpose i/o pin. osc2/clko/ra6 osc2 clko ra6 50 o o i/o ? ? ttl oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clko, which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. general purpose i/o pin. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear). www.datasheet.in
PIC18F8723 family ds39894a-page 20 preliminary ? 2007 microchip technology inc. porta is a bidirectional i/o port. ra0/an0 ra0 an0 30 i/o i ttl analog digital i/o. analog input 0. ra1/an1 ra1 an1 29 i/o i ttl analog digital i/o. analog input 1. ra2/an2/v ref - ra2 an2 v ref - 28 i/o i i ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 27 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 34 i/o i st st digital i/o. timer0 external clock input. ra5/an4/hlvdin ra5 an4 hlvdin 33 i/o i i ttl analog analog digital i/o. analog input 4. high/low-voltage detect input. ra6 see the osc2/clko/ra6 pin. ra7 see the osc1/clki/ra7 pin. table 1-3: pic18f8628/8723 (80-pin) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear). www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 21 PIC18F8723 family portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0/flt0 rb0 int0 flt0 58 i/o i i ttl st st digital i/o. external interrupt 0. pwm fault input for eccpx. rb1/int1 rb1 int1 57 i/o i ttl st digital i/o. external interrupt 1. rb2/int2 rb2 int2 56 i/o i ttl st digital i/o. external interrupt 2. rb3/int3/eccp2/p2a rb3 int3 eccp2 (1) p2a (1) 55 i/o i o o ttl st ? ? digital i/o. external interrupt 3. enhanced capture 2 input/compare 2 output/ pwm2 output. eccp2 pwm output a. rb4/kbi0 rb4 kbi0 54 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb5/kbi1/pgm rb5 kbi1 pgm 53 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. low-voltage icsp? programming enable pin. rb6/kbi2/pgc rb6 kbi2 pgc 52 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp? programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 47 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-3: pic18f8628/8723 (80-pin) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear). www.datasheet.in
PIC18F8723 family ds39894a-page 22 preliminary ? 2007 microchip technology inc. portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 36 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/eccp2/ p2a rc1 t1osi eccp2 (2) p2a (2) 35 i/o i i/o o st cmos st ? digital i/o. timer1 oscillator input. enhanced capture 2 input/compare 2 output/ pwm2 output. eccp2 pwm output a. rc2/eccp1/p1a rc2 eccp1 p1a 43 i/o i/o o st st ? digital i/o. enhanced capture 1 input/compare 1 output/ pwm1 output. eccp1 pwm output a. rc3/sck1/scl1 rc3 sck1 scl1 44 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi1/sda1 rc4 sdi1 sda1 45 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo1 rc5 sdo1 46 i/o o st ? digital i/o. spi data out. rc6/tx1/ck1 rc6 tx1 ck1 37 i/o o i/o st ? st digital i/o. eusart1 asynchronous transmit. eusart1 synchronous clock (see related rx1/dt1). rc7/rx1/dt1 rc7 rx1 dt1 38 i/o i i/o st st st digital i/o. eusart1 asynchronous receive. eusart1 synchronous data (see related tx1/ck1). table 1-3: pic18f8628/8723 (80-pin) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear). www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 23 PIC18F8723 family portd is a bidirectional i/o port. rd0/ad0/psp0 rd0 ad0 psp0 72 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 0. parallel slave port data. rd1/ad1/psp1 rd1 ad1 psp1 69 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 1. parallel slave port data. rd2/ad2/psp2 rd2 ad2 psp2 68 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 2. parallel slave port data. rd3/ad3/psp3 rd3 ad3 psp3 67 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 3. parallel slave port data. rd4/ad4/psp4/sdo2 rd4 ad4 psp4 sdo2 66 i/o i/o i/o o st ttl ttl ? digital i/o. external memory address/data 4. parallel slave port data. spi data out. rd5/ad5/psp5/ sdi2/sda2 rd5 ad5 psp5 sdi2 sda2 65 i/o i/o i/o i i/o st ttl ttl st i 2 c/smb digital i/o. external memory address/data 5. parallel slave port data. spi data in. i 2 c? data i/o. rd6/ad6/psp6/ sck2/scl2 rd6 ad6 psp6 sck2 scl2 64 i/o i/o i/o i/o i/o st ttl ttl st i 2 c/smb digital i/o. external memory address/data 6. parallel slave port data. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c mode. rd7/ad7/psp7/ss2 rd7 ad7 psp7 ss2 63 i/o i/o i/o i st ttl ttl ttl digital i/o. external memory address/data 7. parallel slave port data. spi slave select input. table 1-3: pic18f8628/8723 (80-pin) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear). www.datasheet.in
PIC18F8723 family ds39894a-page 24 preliminary ? 2007 microchip technology inc. porte is a bidirectional i/o port. re0/ad8/rd /p2d re0 ad8 rd p2d 4 i/o i/o i o st ttl ttl ? digital i/o. external memory address/data 8. read control for parallel slave port. eccp2 pwm output d. re1/ad9/wr /p2c re1 ad9 wr p2c 3 i/o i/o i o st ttl ttl ? digital i/o. external memory address/data 9. write control for parallel slave port. eccp2 pwm output c. re2/ad10/cs /p2b re2 ad10 cs p2b 78 i/o i/o i o st ttl ttl ? digital i/o. external memory address/data 10. chip select control for parallel slave port. eccp2 pwm output b. re3/ad11/p3c re3 ad11 p3c (4) 77 i/o i/o o st ttl ? digital i/o. external memory address/data 11. eccp3 pwm output c. re4/ad12/p3b re4 ad12 p3b (4) 76 i/o i/o o st ttl ? digital i/o. external memory address/data 12. eccp3 pwm output b. re5/ad13/p1c re5 ad13 p1c (4) 75 i/o i/o o st ttl ? digital i/o. external memory address/data 13. eccp1 pwm output c. re6/ad14/p1b re6 ad14 p1b (4) 74 i/o i/o o st ttl ? digital i/o. external memory address/data 14. eccp1 pwm output b. re7/ad15/eccp2/ p2a re7 ad15 eccp2 (3) p2a (3) 73 i/o i/o i/o o st ttl st ? digital i/o. external memory address/data 15. enhanced capture 2 input/compare 2 output/ pwm2 output. eccp2 pwm output a. table 1-3: pic18f8628/8723 (80-pin) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear). www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 25 PIC18F8723 family portf is a bidirectional i/o port. rf0/an5 rf0 an5 24 i/o i st analog digital i/o. analog input 5. rf1/an6/c2out rf1 an6 c2out 23 i/o i o st analog ? digital i/o. analog input 6. comparator 2 output. rf2/an7/c1out rf2 an7 c1out 18 i/o i o st analog ? digital i/o. analog input 7. comparator 1 output. rf3/an8 rf3 an8 17 i/o i st analog digital i/o. analog input 8. rf4/an9 rf4 an9 16 i/o i st analog digital i/o. analog input 9. rf5/an10/cv ref rf5 an10 cv ref 15 i/o i o st analog analog digital i/o. analog input 10. comparator reference voltage output. rf6/an11 rf6 an11 14 i/o i st analog digital i/o. analog input 11. rf7/ss1 rf7 ss1 13 i/o i st ttl digital i/o. spi slave select input. table 1-3: pic18f8628/8723 (80-pin) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear). www.datasheet.in
PIC18F8723 family ds39894a-page 26 preliminary ? 2007 microchip technology inc. portg is a bidirectional i/o port. rg0/eccp3/p3a rg0 eccp3 p3a 5 i/o i/o o st st ? digital i/o. enhanced capture 3 input/compare 3 output/ pwm3 output. eccp3 pwm output a. rg1/tx2/ck2 rg1 tx2 ck2 6 i/o o i/o st ? st digital i/o. eusart2 asynchronous transmit. eusart2 synchronous clock (see related rx2/dt2). rg2/rx2/dt2 rg2 rx2 dt2 7 i/o i i/o st st st digital i/o. eusart2 asynchronous receive. eusart2 synchronous data (see related tx2/ck2). rg3/ccp4/p3d rg3 ccp4 p3d 8 i/o i/o o st st ? digital i/o. capture 4 input/compare 4 output/pwm4 output. eccp3 pwm output d. rg4/ccp5/p1d rg4 ccp5 p1d 10 i/o i/o o st st ? digital i/o. capture 5 input/compare 5 output/pwm5 output. eccp1 pwm output d. rg5 see rg5/mclr /v pp pin. table 1-3: pic18f8628/8723 (80-pin) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear). www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 27 PIC18F8723 family porth is a bidirectional i/o port. rh0/a16 rh0 a16 79 i/o i/o st ttl digital i/o. external memory address/data 16. rh1/a17 rh1 a17 80 i/o i/o st ttl digital i/o. external memory address/data 17. rh2/a18 rh2 a18 1 i/o i/o st ttl digital i/o. external memory address/data 18. rh3/a19 rh3 a19 2 i/o i/o st ttl digital i/o. external memory address/data 19. rh4/an12/p3c rh4 an12 p3c (5) 22 i/o i o st analog ? digital i/o. analog input 12. eccp3 pwm output c. rh5/an13/p3b rh5 an13 p3b (5) 21 i/o i o st analog ? digital i/o. analog input 13. eccp3 pwm output b. rh6/an14/p1c rh6 an14 p1c (5) 20 i/o i o st analog ? digital i/o. analog input 14. eccp1 pwm output c. rh7/an15/p1b rh7 an15 p1b (5) 19 i/o i o st analog ? digital i/o. analog input 15. eccp1 pwm output b. table 1-3: pic18f8628/8723 (80-pin) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear). www.datasheet.in
PIC18F8723 family ds39894a-page 28 preliminary ? 2007 microchip technology inc. portj is a bidirectional i/o port. rj0/ale rj0 ale 62 i/o o st ? digital i/o. external memory address latch enable. rj1/oe rj1 oe 61 i/o o st ? digital i/o. external memory output enable. rj2/wrl rj2 wrl 60 i/o o st ? digital i/o. external memory write low control. rj3/wrh rj3 wrh 59 i/o o st ? digital i/o. external memory write high control. rj4/ba0 rj4 ba0 39 i/o o st ? digital i/o. external memory byte address 0 control. rj5/ce rj4 ce 40 i/o o st ? digital i/o external memory chip enable control. rj6/lb rj6 lb 41 i/o o st ? digital i/o. external memory low byte control. rj7/ub rj7 ub 42 i/o o st ? digital i/o. external memory high byte control. v ss 11, 31, 51, 70 p ? ground reference for logic and i/o pins. v dd 12, 32, 48, 71 p ? positive supply for logic and i/o pins. av ss 26 p ? ground reference for analog modules. av dd 25 p ? positive supply for analog modules. table 1-3: pic18f8628/8723 (80-pin) pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p= power i 2 c?/smb = i 2 c/smbus input buffer note 1: alternate assignment for eccp2 when configuration bit, ccp2mx, is cleared (all operating modes except microcontroller mode). 2: default assignment for eccp2 in all operating modes (ccp2mx is set). 3: alternate assignment for eccp2 when ccp2mx is cleared (microcontroller mode only). 4: default assignment for p1b/p1c/p3b/p3c (eccpmx is set). 5: alternate assignment for p1b/p1c/p3b/p3c (eccpmx is clear). www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 29 PIC18F8723 family 2.0 12-bit analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has 12 inputs for the 64-pin devices (pic18f6628/6723) and 16 for the 80-pin devices (pic18f8628/8723). this module allows conversion of an analog input signal to a corresponding 12-bit digital number. the module has five registers: ? a/d result high register (adresh) ? a/d result low register (adresl) ? a/d control register 0 (adcon0) ? a/d control register 1 (adcon1) ? a/d control register 2 (adcon2) the adcon0 register, shown in register 2-1, controls the operation of the a/d module. the adcon1 register, shown in register 2-2, configures the functions of the port pins. the adcon2 register, shown in register 2-3, configures the a/d clock source, programmed acquisition time and justification. register 2-1: adcon0: a/ d control register 0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-2 chs3:chs0: analog channel select bits 0000 = channel 0 (an0) 0001 = channel 1 (an1) 0010 = channel 2 (an2) 0011 = channel 3 (an3) 0100 = channel 4 (an4) 0101 = channel 5 (an5) 0110 = channel 6 (an6) 0111 = channel 7 (an7) 1000 = channel 8 (an8) 1001 = channel 9 (an9) 1010 = channel 10 (an10) 1011 = channel 11 (an11) 1100 = channel 12 (an12) (1,2) 1101 = channel 13 (an13) (1,2) 1110 = channel 14 (an14) (1,2) 1111 = channel 15 (an15) (1,2) bit 1 go/done : a/d conversion status bit when adon = 1 : 1 = a/d conversion in progress 0 = a/d idle bit 0 adon: a/d on bit 1 = a/d converter module is enabled 0 = a/d converter module is disabled note 1: these channels are not implemented on pic18f6628/6723 devices. 2: performing a conversion on unimplemented channels will return a floating input measurement. www.datasheet.in
PIC18F8723 family ds39894a-page 30 preliminary ? 2007 microchip technology inc. register 2-2: adcon1: a/ d control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-4 vcfg1:vcfg0: voltage reference configuration bits bit 3-0 pcfg3:pcfg0: a/d port configuration control bits: a/d v ref + a/d v ref - 00 av dd av ss 01 external v ref +av ss 10 av dd external v ref - 11 external v ref + external v ref - a = analog input d = digital i/o note 1: an15 through an12 are available only on pic18f8628/8723 devices. pcfg<3:0> an15 (1) an14 (1) an13 (1) an12 (1) an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 0000 a aaaaaaaaaaaaaaa 0001 d daaaaaaaaaaaaaa 0010 d ddaaaaaaaaaaaaa 0011 d dddaaaaaaaaaaaa 0100 d ddddaaaaaaaaaaa 0101 d dddddaaaaaaaaaa 0110 d ddddddaaaaaaaaa 0111 d d ddd ddd a a aaaaaa 1000 d dddddddd a aaaaaa 1001 d dddddddddaaaaaa 1010 d ddddddddddaaaaa 1011 d dddddddddddaaaa 1100 d ddddddddddddaaa 1101 d dddddddddddddaa 1110 d dddddddddddddda 1111 d ddddddddddddddd www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 31 PIC18F8723 family register 2-3: adcon2: a/ d control register 2 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 adfm: a/d result format select bit 1 = right justified 0 = left justified bit 6 unimplemented: read as ? 0 ? bit 5-3 acqt2:acqt0: a/d acquisition time select bits 111 = 20 t ad 110 = 16 t ad 101 = 12 t ad 100 = 8 t ad 011 = 6 t ad 010 = 4 t ad 001 = 2 t ad 000 = 0 t ad (1) bit 2-0 adcs2:adcs0: a/d conversion clock select bits 111 = f rc (clock derived from a/d rc oscillator) (1) 110 = f osc /64 101 = f osc /16 100 = f osc /4 011 = f rc (clock derived from a/d rc oscillator) (1) 010 = f osc /32 001 = f osc /8 000 = f osc /2 note 1: if the a/d f rc clock source is selected, a delay of one t cy (instruction cycle) is added before the a/d clock starts. this allows the sleep instruction to be executed before starting a conversion. www.datasheet.in
PIC18F8723 family ds39894a-page 32 preliminary ? 2007 microchip technology inc. the analog reference voltage is software selectable to either the device?s positive and negative supply voltage (v dd and v ss ), or the voltage level on the ra3/an3/ v ref + and ra2/an2/v ref -/cv ref pins. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to oper- ate in sleep, the a/d conversion clock must be derived from the a/d?s internal rc oscillator. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion in progress is aborted. each port pin associated with the a/d converter can be configured as an analog input or a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conversion is com- plete, the result is loaded into the adresh:adresl register pair, the go/done bit (adcon0<1>) is cleared and the a/d interrupt flag bit, adif, is set. the block diagram of the a/d module is shown in figure 2-1. figure 2-1: a/d block diagram (input voltage) v ain v ref + reference voltage av dd (2) vcfg1:vcfg0 chs3:chs0 an7 an6 an5 an4 an3 an2 an1 an0 0111 0110 0101 0100 0011 0010 0001 0000 12-bit a/d v ref - av ss (2) converter an12 (1) an11 an10 an9 an8 1100 1011 1010 1001 1000 note 1: channels an12 through an15 are not available on pic18f6628/6723 devices. 2: i/o pins have diode protection to v dd and v ss . 0 x 1 x x 1 x 0 an15 (1) an14 (1) an13 (1) 1111 1110 1101 www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 33 PIC18F8723 family the value in the adresh:adresl registers is unknown following power-on and brown-out resets and is not affected by any other reset. after the a/d module has been configured as desired, the selected channel must be acquired before the conversion is started. the analog input channels must have their corresponding tris bits selected as an input. to determine acquisition time, see section 2.1 ?a/d acquisition requirements? . after this acquisi- tion time has elapsed, the a/d conversion can be started. an acquisition time can be programmed to occur between setting the go/done bit and the actual start of the conversion. the following steps should be followed to perform an a/d conversion: 1. configure the a/d module: ? configure analog pins, voltage reference and digital i/o (adcon1) ? select a/d input channel (adcon0) ? select a/d acquisition time (adcon2) ? select a/d conversion clock (adcon2) ? turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): ? clear adif bit ? set adie bit ? set gie bit 3. wait the required acquisition time (if required). 4. start conversion: ? set go/done bit (adcon0<1>) 5. wait for a/d conversion to complete by either: ? polling for the go/done bit to be cleared or ? waiting for the a/d interrupt 6. read a/d result registers (adresh:adresl); clear bit, adif, if required. 7. for next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before the next acquisition starts. figure 2-2: a/d transfer function figure 2-3: analog input model digital code output ffeh 003h 002h 001h 000h 0.5 lsb 1 lsb 1.5 lsb 2 lsb 2.5 lsb 4094 lsb 4094.5 lsb 3 lsb analog input voltage fffh 4095 lsb 4095.5 lsb v ain c pin rs anx 5 pf v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = 25 pf v ss v dd 100 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions = sampling switch resistance r ss v dd 6v sampling switch 5v 4v 3v 2v 123 4 (k ) www.datasheet.in
PIC18F8723 family ds39894a-page 34 preliminary ? 2007 microchip technology inc. 2.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 2-3. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor, c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the ana- log input (due to pin leakage current). the maximum recommended impedance for analog sources is 2.5 k . after the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. to calculate the minimum acquisition time, equation 2-1 may be used. this equation assumes that 1/2 lsb error is used (4096 steps for the 12-bit a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. example 2-3 shows the calculation of the minimum required acquisition time, t acq . this calculation is based on the following application system assumptions: c hold = 25 pf rs = 2.5 k conversion error 1/2 lsb v dd =3v rss = 4 k temperature = 85 c (system max.) equation 2-1: acquisition time equation 2-2: a/d minimum charging time equation 2-3: calculating the minimum required acquisition time note: when the conversion is started, the holding capacitor is disconnected from the input pin. t acq = amplifier settling time + holding capacitor charging time + temperature coefficient =t amp + t c + t coff v hold = (v ref ? (v ref /4096)) ? (1 ? e (-t c /c hold (r ic + r ss + r s )) ) or t c = ? (c hold )(r ic + r ss + r s ) ln(1/4096) t acq =t amp + t c + t coff t amp =0.2 s t coff = (temp ? 25 c)(0.02 s/ c) (85 c ? 25 c)(0.02 s/ c) 1.2 s temperature coefficient is only required for temperatures > 25 c. below 25 c, t coff = 0 s. t c = -(c hold )(r ic + r ss + r s ) ln(1/4096) s -(25 pf) (1 k + 4 k + 2.5 k ) ln(0.0002441) s 1.56 s t acq = 0.2 s + 1.56 s + 1.2 s 2.96 s www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 35 PIC18F8723 family 2.2 selecting and configuring acquisition time the adcon2 register allows the user to select an acquisition time that occurs each time the go/done bit is set. it also gives users the option to use an automatically determined acquisition time. acquisition time may be set with the acqt2:acqt0 bits (adcon2<5:3>), which provide a range of 2 to 20 t ad . when the go/done bit is set, the a/d module continues to sample the input for the selected acquisi- tion time, then automatically begins a conversion. since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the go/done bit. manual acquisition is selected when acqt2:acqt0 = 000 . when the go/done bit is set, sampling is stopped and a conversion begins. the user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the go/done bit. this option is also the default reset state of the acqt2:acqt0 bits and is compatible with devices that do not offer programmable acquisition times. in either case, when the conversion is completed, the go/done bit is cleared, the adif flag is set and the a/d begins sampling the currently selected channel again. if an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. 2.3 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 13 t ad per 12-bit conversion. the source of the a/d conversion clock is software selectable. there are seven possible options for t ad : ?2 t osc ?4 t osc ?8 t osc ?16 t osc ?32 t osc ?64 t osc ? internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be as short as possible, but greater than the minimum t ad (see parameter 130 for more information). table 2-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. table 2-1: t ad vs. device operating frequencies a/d clock source (t ad ) assumes t ad min. = 0.8 s operation adcs2:adcs0 maximum f osc 2 t osc 000 2.50 mhz 4 t osc 100 5.00 mhz 8 t osc 001 10.00 mhz 16 t osc 101 20.00 mhz 32 t osc 010 40.00 mhz 64 t osc 110 40.00 mhz rc (1) x11 1.00 mhz (2) note 1: the rc source has a typical t ad time of 2.5 s. 2: for device frequencies above 1 mhz, the device must be in sleep for the entire conversion or a f osc divider should be used instead; otherwise, the a/d accuracy specification may not be met. www.datasheet.in
PIC18F8723 family ds39894a-page 36 preliminary ? 2007 microchip technology inc. 2.4 operation in power-managed modes the selection of the automatic acquisition time and a/d conversion clock is determined in part by the clock source and frequency while in a power-managed mode. if the a/d is expected to operate while the device is in a power-managed mode, the adcs2:adcs0 bits in adcon2 should be updated in accordance with the clock source to be used. the acqt2:acqt0 bits do not need to be adjusted as the adcs2:adcs0 bits adjust the t ad time for the new clock speed. after enter- ing the mode, an a/d acquisition or conversion may be started. once started, the device should continue to be clocked by the same clock source until the conversion has been completed. if desired, the device may be placed into the corresponding idle mode during the conversion. if the device clock frequency is less than 1 mhz, the a/d rc clock source should be selected. operation in sleep mode requires the a/d f rc clock to be selected. if the acqt2:acqt0 bits are set to ? 000 ? and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the sleep instruction and entry to sleep mode. the idlen bit (osccon<7>) must have already been cleared prior to starting the conversion. 2.5 configuring analog port pins the adcon1, trisa, trisf and trish registers all configure the a/d port pins. the port pins needed as analog inputs must have their corresponding tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs3:chs0 bits and the tris bits. note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). analog con- version on pins configured as digital pins can be performed. the voltage on the pin will be accurately converted. 2: analog levels on any pin defined as a dig- ital input may cause the digital input buffer to consume current out of the device?s specification limits. www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 37 PIC18F8723 family 2.6 a/d conversions figure 2-4 shows the operation of the a/d converter after the go/done bit has been set and the acqt2:acqt0 bits are cleared. a conversion is started after the following instruction to allow entry into sleep mode before the conversion begins. figure 2-5 shows the operation of the a/d converter after the go/done bit has been set, the acqt2:acqt0 bits are set to ? 010 ? and a 4 t ad acqui- sition time has been selected before the conversion starts. clearing the go/done bit during a conversion will abort the current conversion. the a/ d result register pair will not be updated with the partially completed a/d conversion sample. this means the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is completed or aborted, a 2t cy wait is required before the next acquisition can be started. after this wait, acquisition on the selected channel is automatically started. 2.7 discharge the discharge phase is used to initialize the value of the holding capacitor. the array is discharged before every sample. this feature helps to optimize the unity gain amplifier, as the circuit always needs to charge the capacitor array, rather than charge/discharge based on previous measure values. figure 2-4: a/d conversion t ad cycles (acqt<2:0> = 000 , t acq = 0 ) figure 2-5: a/d conversion t ad cycles (acqt<2:0> = 010 , t acq = 4 t ad ) note: the go/done bit should not be set in the same instruction that turns on the a/d. code should wait at least 2 s after enabling the a/d before beginning an acquisition and conversion cycle. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go/done bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy ? t ad adresh:adresl are loaded, go/done bit is cleared, adif bit is set, holding capacitor is connected to analog input conversion starts b2 b11 b8 b7 b6 b5 b4 b3 b10 b9 on the following cycle: discharge t ad 13 t ad 12 b0 b1 t ad 1 (typically 200 ns) 1 2 3 4 5 6 7 8 13 set go/done bit (holding capacitor is disconnected) 9 12 conversion starts 1 2 3 4 (holding capacitor continues acquiring input) t acqt cycles t ad cycles automatic acquisition time b0 b11 b8 b7 b6 b5 b4 b1 b10 b9 adresh:adresl are loaded, go/done bit is cleared, adif bit is set, holding capacitor is connected to analog input on the following cycle: t ad 1 discharge 10 11 b3 b2 (typically 200 ns) www.datasheet.in
PIC18F8723 family ds39894a-page 38 preliminary ? 2007 microchip technology inc. 2.8 use of the eccp2 trigger an a/d conversion can be started by the special event trigger of the eccp2 module. this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be programmed as ? 1011 ? and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d acquisition and conversion, and the timer1 (or timer3) counter will be reset to zero. timer1 (or timer3) is reset to automat- ically repeat the a/d acquisition period with minimal software overhead (moving adresh:adresl to the desired location). the appropriate analog input chan- nel must be selected and the minimum acquisition period is either timed by the user, or an appropriate t acq time selected before the special event trigger sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), the special event trigger will be ignored by the a/d module but will still reset the timer1 (or timer3) counter. table 2-2: registers associated with a/d operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif (3) pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if (3) pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie (3) ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip (3) pir2 oscfif cmif ? eeif bcl1if hlvdif tmr3if ccp2if (3) pie2 oscfie cmie ? eeie bcl1ie hlvdie tmr3ie ccp2ie (3) ipr2 oscfip cmip ? eeip bcl1ip hlvdip tmr3ip ccp2ip (3) adresh a/d result register high byte (3) adresl a/d result register low byte (3) adcon0 ? ? chs3 chs2 chs1 chs0 go/done adon (3) adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 (3) adcon2 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 (3) trisa trisa7 (1) trisa6 (1) trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 (3) trisf trisf7 trisf6 trisf5 trisf 4 trisf3 trisf2 trisf1 trisf0 (3) trish (2) trish7 trish6 trish5 trish4 trish3 trish2 trish1 trish0 (3) legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for a/d conversion. note 1: porta<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. when disabled, these bits read as ? 0 ?. 2: these registers are not implemented on pic18f6628/6723 devices. 3: for these reset values, see the ?pic18f8722 family data sheet? (ds39646). www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 39 PIC18F8723 family 3.0 special features of the cpu PIC18F8723 family devices include several features intended to maximize reliability and minimize cost through elimination of external components. these include: ? device id registers 3.1 device id registers the device id registers are ?read-only? registers. they identify the device type and revision to device programmers and can be read by firmware using table reads. table 3-1: device ids note: for additional details on the configuration bits, refer to section 25.1 ?configuration bits? in the ?pic18f8722 family data sheet? (ds39646). device id information presented in this section is for the PIC18F8723 family only. file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value 3ffffeh devid1 dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 xxxx xxxx (1) 3fffffh devid2 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 xxxx xxxx (1) legend: x = unknown note 1: see register 3-1 and register 3-2 for devid values. devid registers are read-only and ca nnot be programmed by the user. www.datasheet.in
PIC18F8723 family ds39894a-page 40 preliminary ? 2007 microchip technology inc. register 3-1: devid1: device id regi ster 1 for PIC18F8723 family devices rrrrrrrr dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 bit 7 bit 0 legend: r = read-only bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state bit 7-5 dev2:dev0: device id bits see register 3-2 for a complete listing. bit 4-0 rev4:rev0: revision id bits these bits are used to indicate the device revision. register 3-2: devid2: device id regi ster 2 for PIC18F8723 family devices rrrrrrrr dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 bit 7 bit 0 legend: r = read-only bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state bit 7-0 dev10:dev3: device id bits dev10:dev3 (devid2<7:0>) dev2:dev0 (devid1<7:5>) device 0100 1001 110 pic18f6628 0100 1010 000 pic18f6723 0100 1001 111 pic18f8628 0100 1010 001 PIC18F8723 www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 41 PIC18F8723 family 4.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any pin with respect to v ss (except v dd and mclr ) ................................................... -0.3v to (v dd + 0.3v) voltage on v dd with respect to v ss ......................................................................................................... -0.3v to +7.5v voltage on mclr with respect to v ss (note 2) ......................................................................................... 0v to +13.25v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma maximum output current sunk by any i/o pin..................................................................................... .....................25 ma maximum output current sourced by any i/o pin .................................................................................. ..................25 ma maximum current sunk by all ports ...................................................................................................................... .200 ma maximum current sourced by all ports ........................................................................................... .......................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd ? i oh } + {(v dd ? v oh ) x i oh } + (v ol x i ol ) 2: voltage spikes below v ss at the rg5/mclr /v pp pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 should be used when applying a ?low? level to the rg5/mclr / v pp pin, rather than pulling this pin directly to v ss . note: other than some basic data, this section documents only the PIC18F8723 family?s specifications that differ from those of the pic18f8722 family devices. for detailed information on the electrical specifications shared by the PIC18F8723 family and pic18f8722 family devices, see the ?pic18f8722 family data sheet? (ds39646). ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. www.datasheet.in
PIC18F8723 family ds39894a-page 42 preliminary ? 2007 microchip technology inc. figure 4-1: PIC18F8723 family voltage-freq uency graph (industrial) figure 4-2: PIC18F8723 family voltage-frequency graph (extended) frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v f max 5.0v 3.5v 3.0v 2.5v PIC18F8723 family 4.2v f max = 20 mhz in 8-bit external memory mode. f max = 40 mhz in all other modes. frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v f max 5.0v 3.5v 3.0v 2.5v 4.2v f max = 20 mhz in 8-bit external memory mode. f max = 25 mhz in all other modes. PIC18F8723 family www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 43 PIC18F8723 family figure 4-3: pic18lf8723 family voltage- frequency graph (industrial) frequency voltage 6.0v 5.5v 4.5v 4.0v 2.0v f max 5.0v 3.5v 3.0v 2.5v in 8-bit external memory mode: note: v ddappmin is the minimum voltage of the pic ? device in the application. 4 mhz 4.2v f max = (9.55 mhz/v) (v ddappmin ? 2.0v) + 4 mhz, if v ddappmin 4.2v; f max = 25 mhz, if v ddappmin > 4.2v. in all other modes: f max = (16.36 mhz/v) (v ddappmin ? 2.0v) + 4 mhz; f max = 40 mhz, if v ddappmin > 4.2v. pic18lf8723 family www.datasheet.in
PIC18F8723 family ds39894a-page 44 preliminary ? 2007 microchip technology inc. table 4-1: a/d converter characteristics: PIC18F8723 family (industrial) param no. sym characteristic min typ max units conditions a01 n r resolution ? ? 12 bit v ref 3.0v a03 e il integral linearity error ? <1 2.0 lsb v dd = 3.0v v ref 3.0v ??2.0lsbv dd = 5.0v a04 e dl differential linearity error ? <1 +1.5/-1.0 lsb v dd = 3.0v v ref 3.0v ??+1.5/-1.0lsbv dd = 5.0v a06 e off offset error ? <1 5 lsb v dd = 3.0v v ref 3.0v ??3lsbv dd = 5.0v a07 e gn gain error ? <1 1.25 lsb v dd = 3.0v v ref 3.0v ??2.00lsbv dd = 5.0v a10 ? monotonicity guaranteed (1) ?v ss v ain v ref a20 v ref reference voltage range (v refh ? v refl ) 3?v dd ? v ss v for 12-bit resolution a21 v refh reference voltage high v ss + 3.0v ? v dd + 0.3v v for 12-bit resolution a22 v refl reference voltage low v ss ? 0.3v ? v dd ? 3.0v v for 12-bit resolution a25 v ain analog input voltage v refl ?v refh v a30 z ain recommended impedance of analog voltage source ??2.5k a50 i ref v ref input current (2) ? ? ? ? 5 150 a a during v ain acquisition. during a/d conversion cycle. note 1: the a/d conversion result never dec reases with an increase in the input voltage and has no missing codes. 2: v refh current is from the ra3/an3/v ref + pin or v dd , whichever is selected as the v refh source. v refl current is from the ra2/an2/v ref -/cv ref pin or v ss , whichever is selected as the v refl source. www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 45 PIC18F8723 family figure 4-4: a/d conversion timing table 4-2: a/d conversion requirements 131 130 132 bsf adcon0, go q4 a/d clk (1) a/d data adres adif go sample old_data sampling stopped done new_data (note 2) 11 10 9 3 2 1 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . t cy 0 param no. symbol characteristic min max units conditions 130 t ad a/d clock period pic18 f xxxx 0.8 12.5 (1) st osc based, v ref 3.0v pic18 lf xxxx 1.4 25.0 (1) sv dd = 3.0v; t osc based, v ref full range pic18 f xxxx ? 1 s a/d rc mode pic18 lf xxxx ? 3 sv dd = 3.0v; a/d rc mode 131 t cnv conversion time (not including acquisition time) (2) 13 14 t ad 132 t acq acquisition time (3) 1.4 ? s 135 t swc switching time from convert sample ? (note 4) 137 t dis discharge time 0.2 ? s note 1: the time of the a/d clock period is dependent on the device frequency and the t ad clock divider. 2: adres registers may be read on the following t cy cycle. 3: the time for the holding capacitor to acquire the ?new? input voltage when the voltage changes full scale after the conversion (v dd to v ss or v ss to v dd ). the source impedance (r s ) on the input channels is 50 . 4: on the following cycle of the device clock. www.datasheet.in
PIC18F8723 family ds39894a-page 46 preliminary ? 2007 microchip technology inc. notes: www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 47 PIC18F8723 family 5.0 packaging information for packaging information, see the ?pic18f8722 family data sheet? (ds39646). www.datasheet.in
PIC18F8723 family ds39894a-page 48 preliminary ? 2007 microchip technology inc. notes: www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 49 PIC18F8723 family appendix a: revision history revision a (august 2007) original data sheet for the PIC18F8723 family of devices. appendix b: device differences the differences between the devices listed in this data sheet are shown in table b-1. table b-1: PIC18F8723 family device differences features pic18f6628 pic18f6723 pic18f8628 PIC18F8723 program memory (bytes) 96k 128k 96k 128k program memory (instructions) 49152 65536 49152 65536 interrupt sources 28 28 29 29 i/o ports ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g ports a, b, c, d, e, f, g, h , j ports a, b, c, d, e, f, g, h , j capture/compare/pwm modules2222 enhanced capture/compare/pwm modules 3333 parallel communications (psp) yes yes yes yes external memory bus no no yes yes 12-bit analog-to-digital module 12 input channels 12 input channels 16 input channels 16 input channels packages 64-pin tqfp 64-pin tqfp 80-pin tqfp 80-pin tqfp www.datasheet.in
PIC18F8723 family ds39894a-page 50 preliminary ? 2007 microchip technology inc. appendix c: conversion considerations this appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. typically, these changes are due to the differences in the process technology used. an example of this type of conversion is from a pic16c74a to a pic16c74b. not applicable appendix d: migration from baseline to enhanced devices this section discusses how to migrate from a baseline device (i.e., pic16c5x) to an enhanced mcu device (i.e., pic18fxxx). the following are the list of modifications over the pic16c5x microcontroller family: not currently available www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 51 PIC18F8723 family appendix e: migration from mid-range to enhanced devices a detailed discussion of the differences between the mid-range mcu devices (i.e., pic16cxxx) and the enhanced devices (i.e., pic18fxxx) is provided in an716, ?migrating designs from pic16c74a/74b to pic18c442 ?. the changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations. this application note is available on our web site, www.microchip.com, as literature number ds00716. appendix f: migration from high-end to enhanced devices a detailed discussion of the migration pathway and differences between the high-end mcu devices (i.e., pic17cxxx) and the enhanced devices (i.e., pic18fxxx) is provided in an726, ?pic17cxxx to pic18cxxx migration ?. this application note is available on our web site, www.microchip.com, as literature number ds00726. www.datasheet.in
PIC18F8723 family ds39894a-page 52 preliminary ? 2007 microchip technology inc. notes: www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 53 PIC18F8723 family index a a/d ...................................................................................... 29 a/d converter interrupt, configuring .......................... 33 acquisition requirements ........................................... 34 adcon0 register....................................................... 29 adcon1 register....................................................... 29 adcon2 register....................................................... 29 adresh register................................................. 29, 32 adresl register ....................................................... 29 analog port pins, configuring..................................... 36 associated registers .................................................. 38 configuring the module............................................... 33 conversion clock (t ad ) .............................................. 35 conversion status (go/done bit) ............................. 32 conversions ................................................................ 37 converter characteristics ........................................... 44 discharge.................................................................... 37 operation in power-managed modes ......................... 36 selecting and configuring acquisition time ............... 35 special event trigger (eccp2) .................................. 38 transfer function........................................................ 33 use of the eccp2 trigger .......................................... 38 absolute maximum ratings ................................................ 41 adcon0 register............................................................... 29 go/done bit.............................................................. 32 adcon1 register............................................................... 29 adcon2 register............................................................... 29 adresh register............................................................... 29 adresl register ......................................................... 29, 32 analog-to-digital converter. see a/d. b block diagrams a/d .............................................................................. 32 analog input model ..................................................... 33 pic18f6628/6723......................................................... 9 pic18f8628/8723....................................................... 10 c compare (eccp2 module) special event trigger.................................................. 38 conversion considerations ................................................. 50 customer change notification service ............................... 55 customer notification service............................................. 55 customer notification system............................................... 5 customer support............................................................... 55 d device differences.............................................................. 49 device id registers ............................................................ 39 device overview features (table)............................................................. 8 special features ........................................................... 7 e electrical characteristics..................................................... 41 equations a/d acquisition time................................................... 34 a/d minimum charging time...................................... 34 calculating the minimum required acquisition time ................................................. 34 errata .................................................................................... 5 external memory interface .................................................... 1 f features summary table ..................................................... 1 i internet address ................................................................. 55 interrupt sources a/d conversion complete .......................................... 33 m microchip internet web site................................................ 55 migration from baseline to enhanced devices.................. 50 migration from high-end to enhanced devices................. 51 migration from mid-range to enhanced devices .............. 51 more information................................................................... 5 customer notification system ...................................... 5 errata............................................................................ 5 o overview external memory interface ........................................... 1 features summary table ............................................. 1 peripheral highlights .................................................... 1 power-managed modes ............................................... 1 special microcontroller features .................................. 1 p packaging information ........................................................ 47 peripheral highlights............................................................. 1 pin diagrams 64-pin tqfp................................................................. 2 80-pin tqfp................................................................. 3 pin functions av dd (64-pin) ............................................................. 18 av dd (80-pin) ............................................................. 28 av ss (64-pin).............................................................. 18 av ss (80-pin).............................................................. 28 osc1/clki/ra7................................................... 11, 19 osc2/clko/ra6 ................................................. 11, 19 ra0/an0............................................................... 12, 20 ra1/an1............................................................... 12, 20 ra2/an2/v ref - .................................................... 12, 20 ra3/an3/v ref + ................................................... 12, 20 ra4/t0cki ........................................................... 12, 20 ra5/an4/hlvdin ................................................ 12, 20 rb0/int0/flt0 .................................................... 13, 21 rb1/int1.............................................................. 13, 21 rb2/int2.............................................................. 13, 21 rb3/int3.................................................................... 13 rb3/int3/eccp2/p2a ............................................... 21 rb4/kbi0.............................................................. 13, 21 rb5/kbi1/pgm..................................................... 13, 21 rb6/kbi2/pgc ..................................................... 13, 21 rb7/kbi3/pgd ..................................................... 13, 21 rc0/t1oso/t13cki ............................................ 14, 22 rc1/t1osi/eccp2/p2a ...................................... 14, 22 rc2/eccp1/p1a.................................................. 14, 22 rc3/sck1/scl1 .................................................. 14, 22 rc4/sdi1/sda1 ................................................... 14, 22 rc5/sdo1............................................................ 14, 22 rc6/tx1/ck1 ....................................................... 14, 22 rc7/rx1/dt1....................................................... 14, 22 rd0/ad0/psp0 .......................................................... 23 rd0/psp0 .................................................................. 15 www.datasheet.in
PIC18F8723 family ds39894a-page 54 preliminary ? 2007 microchip technology inc. rd1/ad1/psp1........................................................... 23 rd1/psp1................................................................... 15 rd2/ad2/psp2........................................................... 23 rd2/psp2................................................................... 15 rd3/ad3/psp3........................................................... 23 rd3/psp3................................................................... 15 rd4/ad4/psp4/sdo2 ................................................ 23 rd4/psp4/sdo2 ........................................................ 15 rd5/ad5/psp5/sdi2/sda2 ....................................... 23 rd5/psp5/sdi2/sda2 ............................................... 15 rd6/ad6/psp6/sck2/scl2 ...................................... 23 rd6/psp6/sck2/scl2 .............................................. 15 rd7/ad7/psp7/ss2 ................................................... 23 rd7/psp7/ss2 ........................................................... 15 re0/ad8/rd /p2d ....................................................... 24 re0/rd /p2d ............................................................... 16 re1/ad9/wr /p2c ...................................................... 24 re1/wr /p2c .............................................................. 16 re2/ad10/cs /p2b ..................................................... 24 re2/cs /p2d ............................................................... 16 re3/ad11/p3c ........................................................... 24 re3/p3c ..................................................................... 16 re4/ad12/p3b ........................................................... 24 re4/p3b ..................................................................... 16 re5/ad13/p1c ........................................................... 24 re5/p1c ..................................................................... 16 re6/ad14/p1b ........................................................... 24 re6/p1b ..................................................................... 16 re7/ad15/eccp2/p2a .............................................. 24 re7/eccp2/p2a ........................................................ 16 rf0/an5 ............................................................... 17, 25 rf1/an6/c2out .................................................. 17, 25 rf2/an7/c1out .................................................. 17, 25 rf3/an8 ............................................................... 17, 25 rf4/an9 ............................................................... 17, 25 rf5/an10/cv ref .................................................. 17, 25 rf6/an11 ............................................................. 17, 25 rf7/ss1 ............................................................... 17, 25 rg0/eccp3/p3a .................................................. 18, 26 rg1/tx2/ck2 ....................................................... 18, 26 rg2/rx2/dt2 ....................................................... 18, 26 rg3/ccp4/p3d .................................................... 18, 26 rg4/ccp5/p1d .................................................... 18, 26 rg5....................................................................... 18, 26 rg5/mclr /v pp .................................................... 11, 19 rh0/a16 ..................................................................... 27 rh1/a17 ..................................................................... 27 rh2/a18 ..................................................................... 27 rh3/a19 ..................................................................... 27 rh4/an12/p3c ........................................................... 27 rh5/an13/p3b ........................................................... 27 rh6/an14/p1c ........................................................... 27 rh7/an15/p1b ........................................................... 27 rj0/ale ...................................................................... 28 rj1/oe ....................................................................... 28 rj2/wrl ..................................................................... 28 rj3/wrh .................................................................... 28 rj4/ba0 ...................................................................... 28 rj5/ce ........................................................................ 28 rj6/lb ........................................................................ 28 rj7/ub ........................................................................ 28 v dd .............................................................................. 28 v dd .............................................................................. 18 v ss .............................................................................. 28 v ss .............................................................................. 18 pinout i/o descriptions pic18f6628/6723 ...................................................... 11 pic18f8628/8723 ...................................................... 19 power-managed modes........................................................ 1 and a/d operation ...................................................... 36 product identification system ............................................. 57 r reader response............................................................... 56 registers adcon0 (a/d control 0)............................................ 29 adcon1 (a/d control 1)............................................ 30 adcon2 (a/d control 2)............................................ 31 devid1 (device id 1)................................................. 40 devid2 (device id 2)................................................. 40 revision history.................................................................. 49 s special features of the cpu .............................................. 39 device id registers .................................................... 39 special microcontroller features .......................................... 1 t timing diagrams a/d conversion........................................................... 45 timing diagrams and specifications a/d conversion requirements ................................... 45 v voltage-frequency graphs extended (PIC18F8723) ............................................. 42 industrial (PIC18F8723).............................................. 42 industrial (pic18lf8723)............................................ 43 w worldwide sales and service offices................................. 58 www address ................................................................... 55 www, on-line support ......... .............................................. 5 www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 55 PIC18F8723 family the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com www.datasheet.in
PIC18F8723 family ds39894a-page 56 preliminary ? 2007 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39894a PIC18F8723 family 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? www.datasheet.in
? 2007 microchip technology inc. preliminary ds39894a-page 57 PIC18F8723 family PIC18F8723 family product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device (1) (2) pic18f6628/6723, pic18f8628/8723, v dd range 4.2v to 5.5v pic18lf6628/6723, pic18lf6628/6723 ( v dd range 2.0v to 5.5v temperature range i= -40 c to +85 c (industrial) e= -40 c to +125 c (extended) package pt = tqfp (thin quad flatpack) pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic18lf6723-i/pt 301 = industrial temp., tqfp package, extended v dd limits, qtp pattern #301. b) pic18f6723-e/pt = extended temp., tqfp package, standard v dd limits. note 1: f = standard voltage range lf = wide voltage range 2: t = in tape and reel tqfp packages only. www.datasheet.in
ds39894a-page 58 preliminary ? 2007 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - penang tel: 60-4-646-8870 fax: 60-4-646-5086 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 06/25/07 www.datasheet.in


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